1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and the semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an element isolation film formed by the LOCOS (Local Oxidation of Silicon) technique.
2. Description of the Related Art
In the field of the method for manufacturing a semiconductor device, the xe2x80x9cPBLxe2x80x9d (Poly-Buffered LOCOS) technique is known as a method used for forming an element isolation film through the LOCOS technique. The element isolation film isolates various semiconductor devices such as MOS transistors. The PBL technique is to form a polycrystalline silicon (hereinafter referred to as xe2x80x9cpoly-Sixe2x80x9d) film previously, which serves as a buffer layer between an oxidation-resisting film and a semiconductor substrate. Specifically, this technique comprises the steps of previously forming an insulating film (pad oxide film) on the entire surface of a substrate, forming a poly-Si film constituting a pad poly-Si film (hereinafter referred to as xe2x80x9cpad poly-Si filmxe2x80x9d) thereon, and forming an oxidation resisting film thereon and performing thermal oxidation.
Now referring to the drawings, an explanation will be given of a method of manufacturing a semiconductor device using the PBL technique.
STEP 1:
As seen from FIG. 3A, a pad oxide film 52 is formed on a semiconductor substrate 51 using the thermal oxidation technique. A pad poly-Si film 53 is formed on the pad oxide film 52 on the CVD (Chemical Vapor Deposition) technique. A silicon nitride film 54 serving as an oxidation resisting film is formed using the CVD technique to form an opening in the region where an element isolation film is to be formed.
STEP 2:
As seen from FIG. 3B, the semiconductor substrate 51 is thermally oxidized using the silicon nitride film 54 as a mask to form an element isolation film 55. At this time, the pad oxide film 52 prevents crystal defects on the surface of the semiconductor substrate beneath a bird""s beak from occurring. The bird""s beak may be generated in such a way that the oxide region of the semiconductor substrate 51 constituting the element isolation film 55 extends more externally than the edge of the opening of the mask and its tip intrudes leanly in between the silicon nitride film 54 and semiconductor substrate 51. The pad poly-Si film 53 suppresses the bird""s beak from extending.
STEP 3:
As seen from FIG. 3C, the pad oxide film 52, pad poly-Si film 53 and silicon nitride film 54 which are located on the region where an element is formed, are removed.
STEP 4:
As seen from FIG. 3D,using the thermal oxidation technique, a gate insulating film 56 is formed, and using the CVD technique, a poly-Si film 57 and a tungsten silicide film 58 are formed.
STEP 5:
As seen from FIG. 3E, using the photolithography, the poly-Si film 57 and tungsten silicide film 58 are patterned to form a gate electrode 59 and wiring 60. Thereafter, using the gate electrode 59 as a mask, impurity ions are injected into the surface of the semiconductor substrate 51 using the ion implantation technique to form a source/drain region (not shown) Further, an interlayer insulating film and wiring are made, thereby completing a semiconductor integrated circuit.
As described above, when the element isolation film is formed using the LOCOS technique, the pad oxide film 52 and pad poly-Si film 53, which are left beneath the silicon nitride film 54 serving as an oxidation resisting film, serve as a buffer layer for suppressing the growth of the bird""s beak. However, they are once removed in the manufacturing process and thereafter the gate insulating film 56 and the poly-Si film 57 constituting the gate electrode are stacked. This increases the number of the manufacturing steps. Further, the element isolation region 55 is formed to swell from the surface of the semiconductor substrate 1 so that a large level difference is produced between the gate electrode 58 formed on the gate insulating film 56 and the wiring 60 formed on the element isolation film 55. Therefore, in the lithography process in the subsequent wiring forming step, the accuracy of adjusting a focal point for exposure is attenuated and hence sufficient pattern accuracy cannot be attained.
The present invention has been accomplished in view of the above circumstance.
An object of the present invention is to reduce the number of steps in a process for manufacturing a semiconductor integrated circuit.
An object of the present invention is to reduce the level difference between a gate electrode on a gate insulating film and a wiring on an element isolation region.
In order to attain the above object, in accordance with the present invention, the pad oxide film and pad poly-Si film are not removed, but used as a part of the gate oxide film and gate electrode, thereby relaxing the above level difference.
Specifically, in accordance with a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a gate insulating film on a semiconductor substrate; forming a first silicon film on the gate insulating film; forming a pattern of an oxidation resisting film on the first silicon film; thermally oxidizing the first silicon film and semiconductor substrate using the pattern of the oxidation resisting film to form an element isolation film; removing the pattern of the oxidation resisting film so that an element area surface surrounded by the element isolation film is exposed; patterning the second and first silicon films so that a wiring of the second silicon film is formed on the element isolation film and a gate electrode composed of the first and second silicon films is formed on the element area surface. In such a method, an oxide film and first silicon film, which are used as the pad insulating film and pad electrode and also used as the buffer layer in LOCOS, are used as the gate insulating film and a part of the gate electrode, respectively. Thus, the level difference between the wiring on the element isolation film and the gate electrode is attenuated to flatten the surface. The gate insulating film and gate electrode are used as they are so that the surface of the element region can be maintained clean without contamination. Thus, the gate insulating film having a high withstand voltage can be obtained, thus attenuating occurrence of poor withstand voltage.
Preferably, the method of manufacturing a semiconductor device further comprises the steps: after the step of forming the second silicon film, forming a metal silicide film on the second silicon film. The step of patterning the second and first silicon films comprises the step of: further patterning the metal silicide film so that a wiring of the second silicon film and the metal silicide film is formed on the element isolation film and the gate electrode composed of-the first and second silicon films and metal silicide film is formed on the element area surface.
In this configuration, the resistance of the wiring and electrode can be reduced.
Preferably, the method of manufacturing a semiconductor device according to the first aspect, further comprises the step: prior to the step of forming the element isolation film, etching a part of a surface of the first silicon film using the oxidation resisting film as at least a part of a mask so that a prescribed thickness of the first silicon film is left.
In this configuration in which the first silicon film is etched to leave a prescribed thickness, the level difference can be further relaxed.
Preferably, in the method of manufacturing a semiconductor device according to the first aspect, the first and second silicon films are made of poly-Si.
Preferably, in the method of manufacturing a semiconductor device according to the first aspect, the first silicon film is a poly-Si film which is more heavily doped than the second silicon film.
In this configuration, the second silicon film, which is changed into silicide, is not required to be highly doped. In addition, since the second silicon film located on the element isolation film is not highly doped, an inconvenience is avoided that impurities are diffused into the surface of the element isolation film to become a film saving slight conductivity such as a PSG film, whereas the wiring, in which the impurity concentration is reduced, becomes to have high resistance.
Preferably, in the method of manufacturing a semiconductor device according to the first aspect, the oxidation resisting film is a silicon nitride film.
In accordance with the second aspect of the preset invention, there is provided a semiconductor device comprising: a semiconductor substrate; an element isolation film formed by the LOCOS technique on a surface of the semiconductor substrate; an element region surrounded by the element isolation film; source/drain regions formed within the element region on the surface of the semiconductor substrate, and a gate insulating film and a gate electrode formed on a channel region between the source/drain regions; and a wiring formed on the element isolation film, wherein the gate electrode is composed of a first silicon film and a second silicon film formed on the first silicon film and the wiring is made of the second silicon film.
Preferably, in the semiconductor device according to the second aspect, a surface of the second silicon film is covered with a metal silicide film.
In accordance with the method of manufacturing a semiconductor device according to the present invention, prior to the LOCOS oxidation for element isolation, the region where an element is to be formed is covered with an insulating film and a pad poly-Si film for forming an electrode pad, and the oxidation resisting film is formed on the resultant surface and heat-treated to form the element isolation film. The pad poly-Si film, without being removed, is used as the first poly-Si film for a part of the gate electrode, and the insulating film (pad oxidation film) is used as the gate insulating film. Therefore, the steps for removing these respective films and forming them again are not required, thus shortening the manufacturing process, reducing the manufacturing cost and manufacturing the manufacturing period.
The gate electrode below the element isolation film includes the first poly-Si film whereas the wiring on the element isolation film does not include the first poly-Si film. The wiring is thinner than the gate electrode so that the level difference between the surfaces of the element isolation film and the element area, thus flattening the surface. Thus, the accuracy of exposure adjustment is improved in the step of using lithography and the overlaid wiring can be easily formed.
Only the first poly-Si film can be highly doped, and the second poly-Si film can be lightly doped. In this structure, the tungsten silicide film with low resistance can be formed on the element isolation film of SiO2. When the poly-Si is highly doped with phosphorus, the element isolation film is prevented from being changed into PSG so that its insulation degree is reduced.
The above and other objects and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.